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PD - 91721C
REPETITIVE AVALANCHE AND dv/dt RATED
HEXFET TRANSISTORS SURFACE MOUNT (LCC-18)
IRFE9110 100V, P-CHANNEL
Product Summary
Part Number IRFE9110 BVDSS -100V RDS(on) 1.2 ID -2.5A
The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. Desinged to be a close replacement for the TO-39 package, the LCC will give designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference.
LCC-18
Features:
n n n n n n n n
Surface Mount Small Footprint Alternative to TO-39 Package Hermetically Sealed Dynamic dv/dt Rating Avalanche Energy Rating Simple Drive Requirements Light Weight
Absolute Maximum Ratings
Parameter
ID @ VGS = -10V, TC = 25C ID @ VGS = -10V, TC = 100C IDM PD @ TC = 25C VGS EAS I AR EAR dv/dt TJ TSTG Continuous Drain Current Continuous Drain Current Pulsed Drain Current Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction Storage Temperature Range Pckg. Mounting Surface Temp. Weight For footnotes refer to the last page -2.5 -1.6 -10 15 0.12 20 102 -14 -55 to 150 300 (for 5 S) 0.42(typical)
Units A
W
W/C
V mJ A mJ V/ns
o
C
g
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10/03/01
IRFE9110
Electrical Characteristics @ Tj = 25C (Unless Otherwise Specified)
Parameter
BVDSS BVDSS/TJ RDS(on) VGS(th) gfs IDSS Drain-to-Source Breakdown Voltage Temperature Coefficient of Breakdown Voltage Static Drain-to-Source On-State Resistance Gate Threshold Voltage Forward Transconductance Zero Gate Voltage Drain Current
Min
-100 -- -- -- -2.0 0.9 -- -- -- -- -- -- -- -- -- -- -- --
Typ Max Units
-- -0.08 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6.1 -- -- 1.2 1.38 -4.0 -- -25 -250 -100 100 15 7.0 8.0 30 60 40 40 -- V V/C V S( ) A
Test Conditions
VGS = 0V, ID = -1.0mA Reference to 25C, ID = -1.0mA VGS = -10V, ID = -1.6A VGS = -10V, ID = -2.5A VDS = VGS, ID = -250A VDS > -15V, IDS = -1.6A VDS= -80V, VGS= 0V VDS =-80V VGS = 0V, TJ = 125C VGS =-20V VGS =20V VGS =-10V, ID= -2.5A VDS =-50V VDD =-50V, ID = -2.5A, VGS =-10V, RG =7.5
IGSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS + LD
Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (`Miller') Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance
nA
nC
ns
nH
Measured from the center of drain pad to center of source pad VGS = 0V, VDS = -25V f = 1.0MHz
Ciss Coss Crss
Input Capacitance Output Capacitance Reverse Transfer Capacitance
-- -- --
214 100 20
-- --
pF
Source-Drain Diode Ratings and Characteristics
Parameter
IS ISM VSD t rr QRR ton Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min Typ Max Units
-- -- -- -- -- -- -- -- -- -- -2.5 -10 -5.5 200 380
Test Conditions
A
V nS c
Tj = 25C, IS = -2.5A, VGS = 0V Tj = 25C, IF = -2.5A, di/dt -100A/s VDD -50V
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
Thermal Resistance
Parameter
RthJC RthJ-PCB Junction to Case Junction to PC Board
Min Typ Max Units
-- -- -- -- 8.3 27
C/W
Test Conditions
Soldered to a copper clad PC board
For footnotes refer to the last page
2
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IRFE9110
100
-I D , Drain-to-Source Current (A)
-I D , Drain-to-Source Current (A)
10
VGS TOP -15V -10V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V
100
10
VGS -15V -10V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V TOP
1
-4.5V
1
-4.5V
20s PULSE WIDTH T = 150 C
J 1 10 100
0.1 0.1
20s PULSE WIDTH T = 25 C
J 1 10 100
0.1 0.1
-VDS , Drain-to-Source Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
10
2.5
-I D , Drain-to-Source Current (A)
TJ = 25 C TJ = 150 C
R DS(on) , Drain-to-Source On Resistance (Normalized)
ID = -2.6A
2.0
1.5
1
1.0
0.5
0.1 4 5 6 7
V DS = -50V 20s PULSE WIDTH 8 9 10
0.0 -60 -40 -20
V GS = -10V
0 20 40 60 80 100 120 140 160
-VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRFE9110
400
-VGS , Gate-to-Source Voltage (V)
C, Capacitance (pF)
300
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
ID = -2.5 A
16
V DS = 80V V DS = 50V V DS = 20V
C iss
200
12
C oss
100
8
4
C rss
0 1 10 100
0 0 4
FOR TEST CIRCUIT SEE FIGURE 13
8 12
VDS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
10
100
-ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY R
DS(on)
-ID , Drain Current (A) I
10
100us 1ms
1
1
TJ = 150 C TJ = 25 C
10ms
0.1 0.0
V GS = 0 V
0.5 1.0 1.5 2.0 2.5 3.0 3.5
0.1
TC = 25 C TJ = 150 C Single Pulse
1 10 100 1000
-VSD ,Source-to-Drain Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFE9110
3.0
V DS VGS
RD
-ID , Drain Current (A)
D.U.T.
+
2.0
VGS Pulse Width 1 s Duty Factor 0.1 %
1.0
Fig 10a. Switching Time Test Circuit
td(on) tr t d(off) tf
VGS 10%
0.0 25 50 75 100 125 150
90%
TC , Case Temperature C) (
Fig 9. Maximum Drain Current Vs. Case Temperature
VDS
Fig 10b. Switching Time Waveforms
10
10
Thermal Response (Z thJC ) Thermal Response (Z thJC )
D = 0.50 D = 0.50 0.20
0.20
0.10
1
1
0.05
0.10 0.05 0.02 0.01 0.02 0.01
0.1
0.1

SINGLE PULSE (THERMAL RESPONSE) SINGLE PULSE (THERMAL RESPONSE)
0.01 0.00001 0.01 0.00001
0.0001 0.0001
0.001
0.001 t1 , Rectangular Pulse t1 , Rectangular Pulse Duration (sec)
Notes: 1. Notes: Duty factor D = t 1 / t 2 1. Duty J = P D = t2 2. Peak Tfactor DM xt 1Z/ thJC + TC 2. Peak TJ = P DM x Z thJC + TC 0.01 0.1 0.01 0.1 Duration (sec)

5
P DM P DM t1 t1 t2 t2
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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-
RG
V DD
1 1
IRFE9110
L
VDS
RG
D .U .T
IA S
EAS , Single Pulse Avalanche Energy (mJ)
300
VD D A D R IV E R
-20V VGS
tp -12V
0.01
TOP BOTTOM ID 1.1A 1.6A 2.5A
200
15V
100
Fig 12a. Unclamped Inductive Test Circuit
IAS
0 25 50 75 100 125 150
Starting TJ , Junction Temperature ( C)
tp V (BR)DSS
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
-12V 12V
.2F .3F
-10V -12V
QGS VG QGD
VGS
-3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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+
D.U.T.
-
VDS
IRFE9110
Repetitive Rating; Pulse width limited by
maximum junction temperature. VDD =-25V, starting TJ = 25C, Peak IL = -2.5A, VGS =- 10V
Foot Notes:
VDD -100V, TJ 150C Suggested RG =7.5 Pulse width 300 s; Duty Cycle 2%
ISD -2.5A, di/dt - 285A/s,
Case Outline and Dimensions -- LCC-18
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 10/01
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